––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
Configuration Register Byte 10, AR = 000ah
DR_0
[1:0]
[3:2]
4
C
Definition
[81:80]
[83:82]
84
Reserved
L_CLK_1 Frequency [1:0]
L_CLK_1 Polarity
L_FS_1 Polarity
5
85
[7:6]
[87:86]
L_FS_1 Position [1:0]
L_CLK_1 Frequency [1:0] (C_ [83:82]) (Read/Write)
00
01
10
11
→
→
→
→
2.048 MHz (Default)
4.096 MHz
8.192 MHz
16.384 MHz
L_CLK_1 Polarity (C_ [84]) (Read/Write)
0
1
→
→
L_CLK_1 Non-Inverted (Default)
L_CLK_1 Inverted
L_FS_1 Polarity (C_ [85]) (Read/Write)
0
1
→
→
L_FS_1 Non-Inverted (Default)
L_FS_1 Inverted
L_FS_1 Position [1:0] (C_ [87:86]) (Read/Write)
00
01
10
11
→
→
→
→
Early - L_FS_1 occurs during the last L_CLK_1 period of the frame (Default)
Straddle - L_FS_1 straddles the frame boundary
Late - L_FS_1 occurs during the first L_CLK_1 period of the frame
Reserved
Oki Semiconductor
27
OKI [ OKI ELECTRONIC COMPONETS ]
