––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ■ ML53612 ■
Configuration Register Byte 16, AR = 0010h
DR_0
C
Definition
0
1
2
3
4
5
6
7
128
129
130
131
132
133
134
135
CT Bus A Error Latch
CT Bus B Error Latch
SCbus Error Latch
MVIP Error Latch
Master PLL Error Latch
Frame Boundary Latch
Reserved
Reserved
CT Bus A Error Latch (C_ [128]) (Read Only)
0
1
→
→
CT Bus A Error Latch False
CT Bus A Error Latch True
CT Bus B Error Latch (C_ [129]) (Read Only)
0
1
→
→
CT Bus B Error Latch False
CT Bus B Error Latch True
SCbus Error Latch (C_ [130]) (Read Only)
0
1
→
→
SCbus Error Latch False
SCbus Error Latch True
MVIP Error Latch (C_ [131]) (Read Only)
0
1
→
→
MVIP Error Latch False
MVIP Error Latch True
Master PLL Error Latch (C_ [132]) (Read Only)
0
1
→
→
Master PLL Error Latch False
Master PLL Error Latch True
Frame Boundary Latch (C_ [133]) (Read Only)
0
1
→
→
Frame Boundary Latch False
Frame Boundary Latch True
Oki Semiconductor
33