NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Table 97.ꢀRegister VGEN5CTL - ADDR 0x70
Name
Bit number
R/W
Default Description
VGEN5
3:0
R/W
0x80
Sets VGEN5 output voltage. See Table 91 for all possible
configurations.
VGEN5EN
4
R/W
0x00
Enables or disables VGEN5 output
• 0 = OFF
• 1 = ON
VGEN5STBY
VGEN5LPWR
UNUSED
5
6
7
R/W
R/W
—
0x00
0x00
0x00
Set VGEN5 output state when in standby. See Table 92.
Enable low-power mode for VGEN5. See Table 92.
unused
Table 98.ꢀRegister VGEN6CTL - ADDR 0x71
Name
Bit number
R/W
Default Description
VGEN6
3:0
R/W
0x80
Sets VGEN6 output voltage. See Table 91 for all possible
configurations.
VGEN6EN
4
R/W
0x00
Enables or disables VGEN6 output
• 0 = OFF
• 1 = ON
VGEN6STBY
VGEN6LPWR
UNUSED
5
6
7
R/W
R/W
—
0x00
0x00
0x00
Set VGEN6 output state when in standby. See Table 92.
Enable low-power mode for VGEN6. See Table 92.
unused
10.4.6.4 External components
Table 99 lists the typical component values for the general purpose LDO regulators.
Table 99.ꢀLDO external components
Regulator
VGEN1
VGEN2
VGEN3
VGEN4
VGEN5
VGEN6
Output capacitor (µF) [1]
2.2
4.7
2.2
4.7
2.2
2.2
[1] Use X5R/X7R ceramic capacitors.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
89 / 137
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