NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Set point
VGENx[3:0]
0011
VGENx output (V)
3
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
10
11
12
13
14
15
1010
1011
1100
1101
1110
1111
In addition to the output voltage configuration, the LDOs can be enabled or disabled
at anytime during normal mode operation, as well as programmed to stay ON or be
disabled when the PMIC enters standby mode. Each regulator has associated I2C bits
for this. Table 92 presents a summary of all valid combinations of the control bits on
VGENxCTL register and the expected behavior of the LDO output.
Table 92.ꢀLDO control (except VGEN1)
VGENxEN
VGENxLPWR
VGENxSTBY
STANDBY[1]
VGENxOUT
Off
0
1
1
1
1
1
X
0
1
X
0
1
X
0
0
1
1
1
X
X
X
0
1
1
On
Low power
On
Off
Low power
[1] STANDBY refers to a standby event.
Table 93 through Table 98 provide a description of all registers necessary to operate all
six general purpose LDO regulators.
Table 93.ꢀRegister VGEN1CTL - ADDR 0x6C
Name
Bit number
R/W
Default Description
VGEN1
3:0
R/W
0x80
Sets VGEN1 output voltage. See Table 90 for all possible
configurations.
VGEN1EN
4
R/W
0x00
Enables or disables VGEN1 output
• 0 = OFF
• 1 = ON
VGEN1STBY
VGEN1LPWR
5
6
R/W
R/W
0x00
0x00
Set VGEN1 output state when in standby. See Table 92.
Enable low-power mode for VGEN1. See Table 92.
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
87 / 137
NXP [ NXP ]
