NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the
regulators do not automatically disable upon a short-circuit detection. However, the
current limiter continues to limit the output current of the regulator. By default, the
REGSCPEN is not set; therefore, at startup none of the regulators are disabled if
an overloaded condition occurs. A fault interrupt, VGENxFAULTI, is generated in an
overload condition regardless of the state of the REGSCPEN bit. See Table 89 for SCP
behavior configuration.
Table 89.ꢀShort-circuit behavior
REGSCPEN[0]
Short-circuit behavior
Current limit
0
1
Shutdown
10.4.6.3 LDO regulator control
Each LDO is fully controlled through its respective VGENxCTL register. This register
enables the user to set the LDO output voltage according to Table 90 for VGEN1 and
VGEN2; and uses the voltage set point in Table 91 for VGEN3 through VGEN6.
Table 90.ꢀVGEN1, VGEN2 output voltage configuration
Set point
VGENx[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
VGENx output (V)
0.800
0
1
0.850
2
0.900
3
0.950
4
1.000
5
1.050
6
1.100
7
1.150
8
1.200
9
1.250
10
11
12
13
14
15
1.300
1.350
1.400
1.450
1.500
1.550
Table 91.ꢀVGEN3/ 4/ 5/ 6 output voltage configuration
Set point
VGENx[3:0]
0000
VGENx output (V)
0
1
2
1.80
1.90
2.00
0001
0010
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
86 / 137
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