NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Symbol
Parameters
Min
Typ
Max
Units
ISWBSTQ
Quiescent current
Auto
µA
—
—
222
206
289
306
RDSONBST
ISWBSTLIM
VSWBSTOSH
MOSFET on resistance
Peak current limit
mΩ
mA
mV
[1]
1400
2200
3200
Startup overshoot
ISWBST = 0.0 mA
—
—
—
—
500
300
VSWBSTTR
VSWBSTTR
tSWBSTTR
tSWBSTTR
Transient load response
mV
mV
µs
ISWBST from 1.0 mA to 100 mA in 1.0 µs
Maximum transient amplitude
Transient load response
ISWBST from 100 mA to 1.0 mA in 1.0 µs
Maximum transient amplitude
—
—
—
—
—
—
300
500
20
Transient load response
ISWBST from 1.0 mA to 100 mA in 1.0 µs
Time to settle 80 % of transient
Transient load response
ms
ISWBST from 100 mA to 1.0 mA in 1.0 µs
Time to settle 80 % of transient
—
ISWBSTHSQ
NMOS Off leakage
µA
ms
SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00
1.0
5.0
tONSWBST
Turn-on time
Enable to 90 % of VSWBST, ISWBST = 0.0 mA
—
—
—
2.0
—
fSWBST
ηSWBST
Switching frequency
2.0
MHz
%
Efficiency
ISWBST = ISWBSTMAX
—
86
—
[1] Only in auto mode
10.4.6 LDO regulators description
This section describes the LDO regulators provided by the PF4210. All regulators use the
main band gap as reference. See Section 10.3 "Bias and references block description",
for more information on the internal reference voltages.
A low-power mode is automatically activated by reducing bias currents when the load
current is less than I_Lmax/5. However, the lowest bias currents may be attained by
forcing the part into its low-power mode by setting the VGENxLPWR bit. The use of this
bit is only recommended when the load is expected to be less than I_Lmax/50, otherwise
performance may be degraded.
When a regulator is disabled, the output is discharged by an internal pull down. The pull
down is also activated when RESETBMCU is low.
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
84 / 137
NXP [ NXP ]
