NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
10.4.5 Boost regulator
SWBST is a boost regulator with a programmable output from 5.0 V to 5.15 V.
SWBST can supply the VUSB regulator for the USB PHY in OTG mode, as well as
the VBUS voltage. Note that the parasitic leakage path for a boost regulator causes
the SWBSTOUT and SWBSTFB voltage to be a Schottky drop below the input voltage
whenever SWBST is disabled. The switching NMOS transistor is integrated on-chip.
Figure 28 shows the block diagram and component connection for the boost regulator.
VIN
SWBSTIN
C
INBST
L
BST
SWBSTLX
V
OBST
DRIVER
D
BST
SWBSTMODE
SWBSTFAULT
OC
2
I C
CONTROLLER
R
INTERFACE
SENSE
V
EP
REFSC
SC
UV
V
REFUV
SWBSTFB
INTERNAL
COMPENSATION
C
OSWBST
Z2
Z1
EA
V
REF
aaa-026497
Figure 28.ꢀBoost regulator architecture
10.4.5.1 SWBST setup and control
Boost regulator control is done through a single register SWBSTCTL described in
Table 86. SWBST is included in the power-up sequence if its OTP power-up timing bits,
SWBST_SEQ[4:0], are not all zeros.
Table 86.ꢀRegister SWBSTCTL - ADDR 0x66
Name
Bit number
R/W
Default Description
SWBST1VOLT
1:0
R/W
0x00
0x02
0x00
Set the output voltage for SWBST
• 00 = 5.000 V
• 01 = 5.050 V
• 10 = 5.100 V
• 11 = 5.150 V
SWBST1MODE
3:2
R
Set the switching mode in normal operation
• 00 = OFF
• 01 = PFM
• 10 = Auto (default) [1]
• 11 = APS
UNUSED
4
—
unused
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
82 / 137
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