NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Parameter
Description
Min
Typ
Max
Unit
tD4
Delay between regulators
SEQ_CLK_SPEED[1:0] = 00
SEQ_CLK_SPEED[1:0] = 01
SEQ_CLK_SPEED[1:0] = 10
SEQ_CLK_SPEED[1:0] = 11
ms
—
—
—
—
0.5
1.0
2.0
4.0
—
—
—
—
tR4
tD5
Rise time of RESETBMCU
—
—
0.2
2.0
—
—
ms
ms
Turn-on delay of RESETBMCU
[1] Assume LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied, then VSNVS turn on delay may extend to a maximum
of 24 ms.
[2] Depends on the external signal driving PWRON.
[3] Default configuration
[4] Rise time is a function of slew rate of regulators and nominal voltage selected.
10.1.2 One time programmability (OTP)
OTP allows the programming of startup configurations for a variety of applications.
Before permanently programming the IC by programming fuses, a configuration may be
prototyped by using the Try Before Buy (TBB) feature. An error correction code (ECC)
algorithm is available to correct a single bit error and to detect multiple bit errors when
fuses are programmed.
The parameters which can be configured by OTP are listed below.
• General: I2C slave address, PWRON pin configuration, startup sequence and timing
• Output voltage, dual/single phase or independent mode configuration, switching
frequency, and soft start ramp rate
• Boost regulator and LDOs: output voltage
Note: When prototyping or programming fuses, ensure register settings are consistent
with the hardware configuration. This is important for the buck regulators, where the
quantity, size, and value of the inductors depend on the configuration (single/ dual phase
or independent mode) and the switching frequency. Additionally, if an LDO is powered by
a buck regulator, it is gated by the buck regulator in the startup sequence.
10.1.2.1 Startup sequence and timing
Each regulator has 5-bit allocated to program its startup time slot from a turn on event;
therefore, each can be placed from position one to thirty-one in the startup sequence.
The all zeros code indicates a regulator is not part of the startup sequence and remains
off (see Table 10). The delay between each position is equal; however, four delay options
are available (see Table 11). The startup sequence terminates at the last programmed
regulator.
Table 10.ꢀStartup sequence
SWxx_SEQ[4:0]/ VGENx_SEQ[4:0]/
VREFDDR_SEQ[4:0]
Sequence
00000
00001
00010
*
Off
SEQ_CLK_SPEED[1:0] * 1
SEQ_CLK_SPEED[1:0] * 2
*
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
18 / 137
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