NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry in the
i.MX processors; VSNVS may be powered from VIN, or from a coin cell.
9.3.2 Control logic
The PF4210 PMIC is fully programmable via the I2C interface. Additional communication
is provided by direct logic interfacing including interrupt and reset. Startup sequence
of the device is selected based on the initial OTP configuration explained in the
Section 10.1 "Startup", or by configuring the Try Before Buy feature to test different
power up sequences before choosing the final OTP configuration.
The PF4210 PMIC has interfaces for the power buttons and a dedicated signaling
interface with the processor. It also ensures supply of critical internal logic and other
circuits from the coin cell, in case of brief interruptions from the main battery. A charger
for the coin cell is included as well.
9.3.2.1 Interface signals
9.3.2.1.1 PWRON
PWRON is an input signal to the IC generating a turn on event. It can be configured to
detect a level, or an edge using the PWRON_CFG bit. See Section 10.4.2.1 "Turn on
events" for more details.
9.3.2.1.2 STANDBY
STANDBY is an input signal to the IC. When it is asserted, the part enters standby mode
and when deasserted, the part exits standby mode. STANDBY can be configured as
active high or active low using the STANDBYINV bit. See Section 10.4.1.3 "Standby
mode" for more details.
Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V
output, a coin cell must be present to provide VSNVS, or the PMIC does not reliably
enter and exit the standby mode.
9.3.2.1.3 RESETBMCU
RESETBMCU is an open drain, active low output configurable for two modes of
operation. In default mode, it is deasserted 2.0 ms to 4.0 ms after the last regulator if the
startup sequence is enabled (see Figure 5). In this mode, the signal can be used to bring
the processor out of reset, or as an indicator that all supplies have been enabled; it is
only asserted for a turn off event.
When configured for fault mode, RESETBMCU is deasserted after the startup sequence
is completed only if no faults occurred during startup. At anytime, if a fault occurs and
persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF4210 is turned off if
the fault persists for more than 100 ms typically.
The PWRON signal restarts the part, though if the fault persists, the sequence described
above is repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD
EN to 1. This register, 0xE8, is located in Table 135 of the register map. To test the fault
mode, the bit may be set during TBB prototyping, or the mode may be permanently
chosen by programming OTP fuses.
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
14 / 137
NXP [ NXP ]
