NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
Registers
Default
Preprogrammed OTP configuration
configuration
A0
3
A1
6
A2
6
A3
6
A4
6
SW4_SEQ
SWBST_VOLT
SWBST_SEQ
VREFDDR_SEQ
VGEN1_VOLT
VGEN1_SEQ
VGEN2_VOLT
VGEN2_SEQ
VGEN3_VOLT
VGEN3_SEQ
VGEN4_VOLT
VGEN4_SEQ
VGEN5_VOLT
VGEN5_SEQ
VGEN6_VOLT
VGEN6_SEQ
—
—
—
—
—
—
—
—
—
—
3
6
6
6
6
—
1.5 V
31
1.5 V
31
1.5 V
31
—
—
—
1.5 V
2
0.9 V
7
0.9 V
7
0.9 V
7
0.9 V
8
—
1.8 V
7
1.8 V
7
1.8 V
7
—
—
—
1.8 V
3
1.8 V
5
1.8 V
5
1.8 V
5
1.8 V
5
2.5 V
3
3.3 V
7
3.3 V
7
3.3 V
7
—
—
2.8 V
3
2.8 V
31
2.8 V
31
2.8 V
31
—
—
PU CONFIG, SEQ_CLK_
SPEED
1.0 ms
2.0 ms
2.0 ms
2.0 ms
2.0 ms
PU CONFIG, SWDVS_
CLK
6.25 mV/μs
1.5625 mV/μs
1.5625 mV/μs
Level sensitive
1.5625 mV/μs
1.5625 mV/μs
PU CONFIG, PWRON
SW1AB CONFIG
SW1C CONFIG
SW2 CONFIG
SW3A CONFIG
SW3B CONFIG
SW4 CONFIG
PG EN
SW1AB single phase, SW1C independent mode, 2.0 MHz
2.0 MHz
2.0 MHz
SW3AB single phase mode, 2.0 MHz
2.0 MHz
No VTT, 2.0 MHz
RESETBMCU in default mode
Notes:
• Keep bit SW2ILIM = 0 for A1, A2, A3 and A4 for max. rated output load current.
• Keep bit SW3xILIM = 0 for A1, A2, A3 and A4 for max. rated output load current.
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
16 / 137
NXP [ NXP ]
