NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
9.3.2.1.4 SDWNB
SDWNB is an open drain, active low output notifying the processor of an imminent PMIC
shut down. It is asserted low for one 32 kHz clock cycle before powering down and is
then deasserted in the OFF state.
9.3.2.1.5 INTB
INTB is an open drain, active low output. It is asserted when any fault occurs, provided
the fault interrupt is unmasked. INTB is deasserted after the fault interrupt is cleared by
software, which requires writing a 1 to the fault interrupt bit.
10 Functional block requirements and behaviors
10.1 Startup
The PF4210 can be configured to start up from either the internal OTP configuration,
or with a hard coded configuration built into the device. The internal hard coded
configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kΩ
resistor. The OTP configuration is enabled by connecting VDDOTP to GND.
For NP (nonprogrammed) devices, selecting the OTP configuration causes the
PF4210 to not start up. However, the PF4210 can be controlled through the I2C port
for prototyping and programming. Once programmed, the NP device starts up with the
customer programmed configuration.
10.1.1 Device startup configuration
Table 8 shows the default configuration for all devices and the preprogrammed OTP
configurations.
Table 8.ꢀStartup configuration
Registers
Default
Preprogrammed OTP configuration
configuration
A0
A1
A2
0x08
1.0 V
0.9 V
4
A3
A4
Default I2C addr
VSNVS_VOLT
SW1AB_VOLT
SW1AB_SEQ
SW1C_VOLT
SW1C_SEQ
SW2_VOLT
3.0 V
1.375 V
1
1.0 V
0.9 V
4
1.0 V
0.9 V
4
1.0 V
0.9 V
3
1.375 V
1
0.9 V
4
0.9 V
4
0.9 V
4
0.9 V
4
3.0 V
2
1.1 V
6
1.2 V
6
1.35 V
6
1.2 V
6
SW2_SEQ
SW3A_VOLT
SW3A_SEQ
SW3B_VOLT
SW3B_SEQ
SW4_VOLT
1.5 V
3
1.0 V
4
1.0 V
4
1.0 V
4
0.9 V
4
1.5 V
3
1.0 V
4
1.0 V
4
1.0 V
4
0.9 V
4
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
15 / 137
NXP [ NXP ]
