NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
LICELL
UVDET
td
tr
1
VIN
VSNVS*
PWRON
SW1A/B
SW1C
1
1.0 V
td
2
tr
2
td
3
tr
3
td
4
tr
3
SW2
VGEN2
tr
3
td
4
SW3A/B
SW4
VREFDDR
VGEN4
VGEN5
VGEN6
td
tr
4
5
RESETBMCU
*VSNVS starts from 1.0 V if LICELL is valid before VIN
aaa-026474
Figure 5.ꢀDefault startup sequence A0
Table 9.ꢀDefault startup sequence timing
Parameter
Description
Min
—
Typ
5.0
3.0
Max
—
Unit
[1]
tD1
tR1
tD2
tR2
tD3
Turn-on delay of VSNVS
Rise time of VSNVS
User determined delay
Rise time of PWRON
ms
ms
ms
ms
ms
—
—
—
1.0
—
[2]
—
—
Turn-on delay of first regulator
SEQ_CLK_SPEED[1:0] = 00
SEQ_CLK_SPEED[1:0] = 01 [3]
SEQ_CLK_SPEED[1:0] = 10
SEQ_CLK_SPEED[1:0] = 11
—
—
—
—
2.0
2.5
4.0
7.0
—
—
—
—
[4]
tR3
Rise time of regulators
—
0.2
—
ms
PF4210
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© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
17 / 137
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