NXP Semiconductors
PF4210
14-channel power management integrated circuit (PMIC) for audio/video applications
9.2 Functional block diagram
PF4210 functional internal block diagram
OTP startup configuration
Power generation
Switching regulators
Linear regulators
Voltage
VGEN1
(0.8 V to 1.55 V, 100 mA)
SW1A/B/C
(0.3 V to 1.875 V)
Configurable 4.5 A or
2.5 A + 2.0 A
Sequence
and timing
Phasing and
frequency selection
VGEN2
(0.8 V to 1.55 V, 250 mA)
Bias and references
Internal core voltage reference
DDR voltage reference
VGEN3
(1.8 V to 3.3 V, 100 mA)
SW2
(0.4 V to 3.3 V), 2.5 A
VGEN4
(1.8 V to 3.3 V, 350 mA)
SW3A/B
(0.4 V to 3.3 V)
Configurable 3.0 A or
1.5 A + 1.5 A
Logic and control
Parallel MCU
interface
VGEN5
Regulator control
(1.8 V to 3.3 V, 100 mA)
SW4
2
I C communication and registers
VGEN6
(0.4 V to 3.3 V, 1.0 A)
(0.8 V to 1.55 V, 200 mA)
Fault detection and protection
Boost regulator
(5.0 V to 5.15 V, 600 mA)
USB OTG supply
Thermal
Current limit
Short circuit
aaa-026473
Figure 4.ꢀFunctional block diagram
9.3 Functional description
9.3.1 Power generation
The PF4210 PMIC features four buck regulators (up to six independent outputs), one
boost regulator, six general purpose LDOs, one switch/LDO combination and a DDR
voltage reference to supply voltage for the application processor and peripheral devices.
The number of independent buck regulator outputs can be configured from four to six,
thereby providing flexibility to operate with higher current capability, or to operate as
independent outputs for applications requiring more voltage rails with lower current
demands. SW1 and SW3 regulators can be configured as single/dual phase and/or
independent converters. One of the buck regulators, SW4, can also operate as a tracking
regulator when used for memory termination.
The buck regulators provide supply to processor cores and to other low voltage circuits
such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply
rail adjustments for the processor cores and/or other circuitry.
Depending on the system power path configuration, the six general purpose LDO
regulators can be directly supplied from the main input supply or from the switching
regulators to power peripherals, such as audio, camera, bluetooth, and wireless LAN.
A specific VREFDDR voltage reference is included to provide an accurate reference
voltage for DDR memories operating with or without VTT termination. The VSNVS block
PF4210
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2018. All rights reserved.
Data sheet: technical data
Rev. 2.0 — 14 November 2018
13 / 137
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