NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Field
Description
Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition
operation produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and branch,
shift, and rotate — also clear or set the carry/borrow flag.
0
C
0ꢀNo carry out of bit 7
1ꢀCarry out of bit 7
10.4 Addressing modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08,
all memory, status and control registers, and input/output (I/O) ports share a single 64-
Kbyte linear address space so a 16-bit binary address can uniquely identify any memory
location. This arrangement means that the same instructions that access variables in
RAM can also be used to access I/O and control registers or nonvolatile program space.
Some instructions use more than one addressing mode. For instance, move instructions
use one addressing mode to specify the source operand and a second addressing mode
to specify the destination address. Instructions such as BRCLR, BRSET, CBEQ, and
DBNZ use one addressing mode to specify the location of an operand for a test and then
use relative addressing mode to specify the branch destination address when the tested
condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed
in the instruction set tables is the addressing mode needed to access the operand to be
tested, and relative addressing mode is implied for the branch destination.
10.4.1 Inherent addressing mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located
within CPU registers so the CPU does not need to access memory to get any operands.
10.4.2 Relative addressing mode (REL)
Relative addressing mode is used to specify the destination location for branch
instructions. A signed 8-bit offset value is located in the memory location immediately
following the opcode. During execution, if the branch condition is true, the signed offset
is sign-extended to a 16-bit value and is added to the current contents of the program
counter, which causes program execution to continue at the branch destination address.
10.4.3 Immediate addressing mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is
included in the object code immediately following the instruction opcode in memory.
In the case of a 16-bit immediate operand, the high-order byte is located in the next
memory location after the opcode, and the low-order byte is located in the next memory
location after that.
10.4.4 Direct addressing mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address
in the direct page (0x0000–0x00FF). During execution a 16-bit address is formed by
concatenating an implied 0x00 for the high-order half of the address and the direct
address from the instruction to get the 16-bit address where the desired operand is
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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