NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
full 16-bit value in H:X as an index reference pointer; however, for compatibility with the
earlier M68HC05 Family, some instructions operate only on the low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used
to hold 8-bit data values. X can be cleared, incremented, decremented, complemented,
negated, shifted, or rotated. Transfer instructions allow data to be transferred from A or
transferred to A where arithmetic and logical operations can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset.
Reset has no effect on the contents of X.
10.3.3 Stack pointer (SP)
This 16-bit address pointer register points at the next available location on the automatic
last-in-first-out (LIFO) stack. The stack may be located anywhere in the 64-Kbyte address
space that has RAM and can be any size up to the amount of available RAM. The stack
is used to automatically save the return address for subroutine calls, the return address
and CPU registers during interrupts, and for local variables. The AIS (add immediate to
stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most often
used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family.
HCS08 programs normally change the value in SP to the address of the last location
(highest address) in on-chip RAM during reset initialization to free up direct page RAM
(from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the
M68HC05 Family and is seldom used in new HCS08 programs because it only affects
the low-order half of the stack pointer.
10.3.4 Program counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction
or operand to be fetched.
During normal program execution, the program counter automatically increments to the
next sequential memory location every time an instruction or operand is fetched. Jump,
branch, interrupt, and return operations load the program counter with an address other
than that of the next sequential location. This is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at
0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that
will be executed after exiting the reset state.
10.3.5 Condition code register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that
indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to
1. The following paragraphs describe the functions of the condition code bits in general
terms. For a more detailed explanation of how each instruction sets the CCR bits, refer to
the HCS08 Family Reference Manual, volume 1, NXP Semiconductors document order
number HCS08RMv1.
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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