NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not
masked by the global I bit in the CCR and it is associated with an instruction opcode
within the program so it is not asynchronous to program execution.
10.5.3 WAIT mode operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the
clocks to the CPU to reduce overall power consumption while the CPU is waiting for the
interrupt or reset event that will wake the CPU from WAIT mode. When an interrupt or
reset event occurs, the CPU clocks will resume and the interrupt or reset event will be
processed normally.
If a serial BACKGROUND command is issued to the MCU through the BACKGROUND
DEBUG interface while the CPU is in WAIT mode, CPU clocks will resume and the CPU
will enter ACTIVE BACKGROUND mode where other serial BACKGROUND commands
can be processed. This ensures that a host development system can still gain access to
a target MCU even if it is in WAIT mode.
10.5.4 STOP mode operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during
STOP mode to minimize power consumption. In such systems, external circuitry is
needed to control the time spent in STOP mode and to issue a signal to wakeup the
target MCU when it is time to resume processing. Unlike the earlier M68HC05 and
M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of clocks running
in STOP mode. This optionally allows an internal periodic signal to wake the target MCU
from STOP mode.
When a host debug system is connected to the BACKGROUND DEBUG pin (BKGD) and
the ENBDM control bit has been set by a serial command through the BACKGROUND
interface (or because the MCU was reset into ACTIVE BACKGROUND mode), the
oscillator is forced to remain active when the MCU enters STOP mode. In this case, if
a serial BACKGROUND command is issued to the MCU through the BACKGROUND
DEBUG interface while the CPU is in STOP mode, CPU clocks will resume and the CPU
will enter ACTIVE BACKGROUND mode where other serial BACKGROUND commands
can be processed. This ensures that a host development system can still gain access to
a target MCU even if it is in STOP mode.
Recovery from STOP mode depends on the particular HCS08 and whether the oscillator
was stopped in STOP mode. Refer to the Section 5 "Modes of operation" for more
details.
10.5.5 BGND instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would
not be used in normal user programs because it forces the CPU to stop processing
user instructions and enter the ACTIVE BACKGROUND mode. The only way to resume
execution of the user program is through reset or by a host debug system issuing a GO,
TRACE1, or TAGGO serial command through the BACKGROUND DEBUG interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint
address with the BGND opcode. When the program reaches this breakpoint address, the
CPU is forced to ACTIVE BACKGROUND mode rather than continuing the user program.
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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