NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
10.5 Special operations
The CPU performs a few special operations that are similar to instructions but do not
have opcodes like other CPU instructions. In addition, a few instructions such as STOP
and WAIT directly affect other MCU circuitry. This section provides additional information
about these operations.
10.5.1 Reset sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the
COP (computer operating properly) watchdog, or by assertion of an external active-low
reset pin. When a reset event occurs, the CPU immediately stops whatever it is doing
(the MCU does not wait for an instruction boundary before responding to a reset event).
For a more detailed discussion about how the MCU recognizes resets and determines
the source, refer to Section 7 "Reset, interrupts and system configuration".
The reset event is considered concluded when the sequence to determine whether the
reset came from an internal source is done and when the reset pin is no longer asserted.
At the conclusion of a reset event, the CPU performs a 6-cycle sequence to fetch the
reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for
execution of the first program instruction.
10.5.2 Interrupt sequence
When an interrupt is requested, the CPU completes the current instruction before
responding to the interrupt. At this point, the program counter is pointing at the start of
the next instruction, which is where the CPU should return after servicing the interrupt.
The CPU responds to an interrupt by performing the same sequence of operations as
for a software interrupt (SWI) instruction, except the address used for the vector fetch is
determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the
interrupt vector to fill the instruction queue in preparation for execution of the first
instruction in the interrupt service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent
other interrupts while in the interrupt service routine. Although it is possible to clear the I
bit with an instruction in the interrupt service routine, this would allow nesting of interrupts
(which is not recommended because it leads to programs that are difficult to debug and
maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index
register pair (H) is not saved on the stack as part of the interrupt sequence. The user
must use a PSHH instruction at the beginning of the service routine to save H and then
use a PULH instruction just before the RTI that ends the interrupt service routine. It is not
necessary to save H if you are certain that the interrupt service routine does not use any
instructions or auto-increment addressing modes that might change the value of H.
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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