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F87EHHD 参数 Datasheet PDF下载

F87EHHD图片预览
型号: F87EHHD
PDF下载: 下载PDF文件 查看货源
内容描述: [FXTH87E, Family of Tire Pressure Monitor Sensors]
分类和应用:
文件页数/大小: 183 页 / 1700 K
品牌: NXP [ NXP ]
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NXP Semiconductors  
FXTH87E  
FXTH87E, Family of Tire Pressure Monitor Sensors  
register is used to select whether the resistor is a pullup (KBEDG[3:0] = 0) or a pulldown  
(KBEDG[3:0] = 1).  
9.6.4 KBI initialization  
When a keyboard interrupt pin is first enabled it is possible to get a false keyboard  
interrupt flag. To prevent a false interrupt request during keyboard initialization, the user  
should do the following:  
1. Mask keyboard interrupts by clearing KBIE in KBISC.  
2. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES.  
3. If using internal pullup/pulldown device, configure the associated pullup enable bits in  
PTAPE[3:0].  
4. Enable the KBI pins by setting the appropriate KBIPE[3:0] bits in KBIPE.  
5. Write to KBACK in KBISC to clear any false interrupts.  
6. Set KBIE in KBISC to enable interrupts.  
10 Central processing unit  
10.1 Introduction  
This section provides summary information about the registers, addressing modes, and  
instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to  
the HCS08 Family Reference Manual, volume 1, NXP Semiconductor document order  
number HCS08RMV1/D.  
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.  
Several instructions and enhanced addressing modes were added to improve C compiler  
efficiency and to support a new BACKGROUND DEBUG system which replaces the  
monitor mode of earlier M68HC08 microcontrollers (MCU).  
10.2 Features  
Features of the HCS08 CPU include:  
Object code fully upward-compatible with M68HC05 and M68HC08 Families  
All registers and memory are mapped to a single 64-Kbyte address space  
16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)  
16-bit index register (H:X) with powerful indexed addressing modes  
8-bit accumulator (A)  
Many instructions treat X as a second general-purpose 8-bit register  
Seven addressing modes:  
Inherent — Operands in internal registers  
Relative — 8-bit signed offset to branch destination  
Immediate — Operand in next object code byte(s)  
Direct — Operand in memory at 0x0000–0x00FF  
Extended — Operand anywhere in 64-Kbyte address space  
Indexed relative to H:X — Five submodes including auto-increment  
Indexed relative to SP — Improves C efficiency dramatically  
Memory-to-memory data move instructions with four address mode combinations  
FXTH87ERM  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2019. All rights reserved.  
Reference manual  
Rev. 5.0 — 4 February 2019  
62 / 183  
 
 
 
 
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