NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
condition code register
V
1
1
H
I
N
Z
C
CCR
Carry
Zero
Negative
Interrupt mask
Half-carry (from bit 3)
Two's complement overflow
aaa-028005
Figure 17.ꢀCondition code register
Table 74.ꢀCCR register field descriptions
Field
Description
Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s
complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and
BLT use the overflow flag.
7
V
0ꢀNo overflow
1ꢀOverflow
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry
(ADC) operation. The half-carry flag is required for binary-coded decimal (BCD)
arithmetic operations. The DAA instruction uses the states of the H and C
condition code bits to automatically add a correction value to the result from a
previous ADD or ADC on BCD operands to correct the result to a valid BCD value.
4
H
0ꢀNo carry between bits 3 and 4
1ꢀCarry between bits 3 and 4
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts
are disabled. CPU interrupts are enabled when the interrupt mask is cleared.
When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU
registers are saved on the stack, but before the first instruction of the interrupt
service routine is executed.
3
I
Interrupts are not recognized at the instruction boundary after any instruction that
clears I (CLI or TAP). This ensures that the next instruction after a CLI or TAP will
always be executed without the possibility of an intervening interrupt, provided I
was set.
0ꢀInterrupts enabled
1ꢀInterrupts disabled
Negative Flag — The CPU sets the negative flag when an arithmetic operation,
logic operation, or data manipulation produces a negative result, setting bit 7 of the
result. Simply loading or storing an 8-bit or 16-bit value causes N to be set if the
most significant bit of the loaded or stored value was 1.
2
N
0ꢀNon-negative result
1ꢀNegative result
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of 0x00 or 0x0000. Simply
loading or storing an 8-bit or 16-bit value causes Z to be set if the loaded or stored
value was all 0s.
1
Z
0ꢀNon-zero result
1ꢀZero result
FXTH87ERM
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