NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
[2] This bit can be written only one time after reset. Additional writes are ignored.
Table 44.ꢀSPMSC1 register field descriptions
Field
Description
7
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect
event.
LVDF
6
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return logic 0.
LVDACK
Low-Voltage Detect Interrupt Enable — This read/write bit enables hardware interrupt requests for LVDF.
0ꢀHardware interrupt disabled (use polling)
5
LVDIE
1ꢀRequest a hardware interrupt when LVDF = 1
Low-Voltage Detect Reset Enable — This read/write bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
4
0ꢀLVDF does not generate hardware resets
1ꢀForce an MCU reset when LVDF = 1
LVDRE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-
voltage detect function operates when the MCU is in STOP mode.
3
0ꢀLow-voltage detect disabled during STOP mode
1ꢀLow-voltage detect enabled during STOP mode
LVDSE
Low-Voltage Detect Enable — This read/write bit enables low-voltage detect logic and qualifies the
operation of other bits in this register.
2
0ꢀLVD logic disabled
1ꢀLVD logic enabled
LVDE
0
Reserved Bit — This bit is reserved should not be altered by the user. Any read returns a logical zero. Any
write should be a logical zero.
Reserved
Band gap Buffer Enable — The BGBE bit is used to enable an internal buffer for the band gap voltage
reference for use by the ADC module on one of its internal channels.
0
0ꢀBand gap buffer disabled
1ꢀBand gap buffer enabled
BGBE
7.11.5 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to configure the STOP mode behavior of the MCU.
Table 45.ꢀSystem power management status and control 2 register (SPMSC2) (address $180A)
Bit
R
7
6
5
4
3
2
0
1
0
0
0
0
PDF
0
PDC[1]
0
W
PPDACK
Power-
on reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Any other
reset
U
U
= Reserved
[1] This bit can be written only one time after reset. Additional writes are ignored.
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
48 / 183
NXP [ NXP ]
