NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Delay Timing (ms)
RTIS0
RTIS2
RTIS1
(Dependent on 1-kHz LFO)
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
8
16
32
64
128
7.10 Temperature sensor and restart system
The FXTH87E has two temperature sensing mechanisms. The first is an accurate sensor
which is accessible through the ADC10 channel 1. The second is a less accurate, very
low power sensor which generates a wakeup from STOP1 when the temperature crosses
its threshold of detection. This is the temperature restart wakeup which is used as
follows:
1. The temperature restart wakeup is enabled by software following detection of an over
temperature condition using the temperature sensor connected to the ADC10.
2. User software enables the temperature restart detector and then instructs the MCU to
enter STOP1 mode to halt execution during the out-of-range temperature condition.
3. When the temperature crosses the temperature restart threshold back into the normal
range of operation, a wakeup is generated to wake the MCU. Exit from STOP1 will
reset the device.
The temperature sensor is enabled whenever the ADC10 is enabled. The temperature
restart wakeup is enabled by setting the TRE bit in SIMOPT1 register and whether the
detector interrupts the MCU from a very low or a very high temperature is determined by
the TRH bit in the SIMOPT1 register.
7.11 Reset, interrupt and system control registers and bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-
page register space are related to reset and interrupt systems.
7.11.1 System Reset Status Register (SRS)
The SRS register at $1800 includes seven read-only status flags to indicate the source
of the most recent reset. When a debug host forces reset by writing 1 to BDFR in the
SBDFR register, none of the status bits in SRS will be set. Writing any value to this
register address clears the COP watchdog timer without affecting the contents of this
register. The reset state of these bits depends on what caused the MCU to reset.
Table 37.ꢀSystem reset status register (SRS) (address $1800)
Bit
R
7
6
5
4
3
2
1
0
0
POR
PIN
COP
ILOP
ILAD
PWU
LVD
W
POR Reset
LVD Reset
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
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