NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
7.11.3 System Operation Register 2 (SIMOPT2)
The following clock source and frequency selections are available using the system
option register 2 as shown in Table 41.
Table 41.ꢀSystem option register 2 (SIMOPT2) (address $1803)
Bit
R
7
6
5
COPT[2:0]
1
4
3
LFOSEL
0
2
TCLKDIV
0
1
0
BUSCLKS[1:0]
W
Reset
0
1
1
0
0
= Reserved
Table 42.ꢀSIMOPT2 register field descriptions
Field
Description
7
Reserved
Reserved
COP Watchdog Time Out — These control bits select the timeout period for the COP watchdog timer
as given in Table 28. These bits are set by an MCU reset to select the longest watchdog timeout
period. These bits are write-once after power up.
6:4
COPT[2:0]
TPM1 Channel 0 Clock Source — This bit determines which signal is connected to the TPM1 Channel
0, see Section 11 "Timer Pulse-Width Module".
3
0ꢀSelect clock input driven by PTA2.
1ꢀSelect clock input driven by the LFO.
LFOSEL
TPM1 Channel 0 Clock Source Divider — The divider for the clock source for TPM1 Channel 0, see
Section 11 "Timer Pulse-Width Module".
2
0ꢀSelect RFM Dx clock source divided by 1.
1ꢀSelect RFM Dx clock source divided by 8.
TCLKDIV
Bus Clock Select — Bus clock frequency selection by changing HFO FLL ratio as shown in Figure 2.
The bus clock frequency is always the HFO frequency divided by two. These bits are cleared by a
reset and can be written at any time.
1:0
00ꢀBus Frequency = 4 MHz (HFO = 8 MHz)
01ꢀBus Frequency = 2 MHz (HFO = 4 MHz)
10ꢀBus Frequency = 1 MHz (HFO = 2 MHz)
11ꢀBus Frequency = 0.5 MHz (HFO = 1 MHz)
BUSCLKS[1:0]
7.11.4 System Power Management Status and Control 1 Register (SPMSC1)
Table 43.ꢀSystem power management status and control 1 register (SPMSC1) (address $1809)
Bit
R
7
6
5
LVDIE
0
4
LVDRE[2]
1
3
LVDSE
1
2
LVDE[2]
1
1[1]
0
0
BGBE
0
LVDF
0
LVDACK
0
W
Reset
0
0
= Reserved
[1] Bit 1 is a reserved bit that must always be written to 0.
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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