NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Table 53.ꢀSIMSES register field descriptions
Field
Description
7-6
Reserved Bits — These bits are reserved for NXP firmware control. Application software shall assure that
this bit is never overwritten.
Reserved
Keyboard Flag — This bit indicates that any keyboard pin caused the last exit from STOP mode.
0ꢀKeyboard pin did not cause the last exit from STOP mode
5
KBF
1ꢀKeyboard pin caused the last exit from STOP mode
IRQ Flag — This bit indicates that IRQ pin caused the last exit from STOP mode.
0ꢀIRQ pin did not cause the last exit from STOP mode
4
IRQF
1ꢀIRQ pin caused the last exit from STOP mode
Temperature Restart Flag — This bit indicates that the temperature restart module caused the last exit from
STOP mode.
3
0ꢀTR module did not cause the last exit from STOP mode
1ꢀTR module caused the last exit from STOP mode
TRF
PWU Flag — This bit indicates that the PWU module caused the last exit from STOP mode.
0ꢀPWU module did not cause the last exit from STOP mode
2
PWUF
1ꢀPWU module caused the last exit from STOP mode
LFR Flag — This bit indicates that the LFR module caused the last exit from STOP mode.
0ꢀLFR module did not cause the last exit from STOP mode
1
LFF
1ꢀLFR module caused the last exit from STOP mode
RFM Flag — This bit indicates that the RFM module caused the last exit from STOP mode.
0ꢀRFM module did not cause the last exit from STOP mode
0
RFF
1ꢀRFM module caused the last exit from STOP mode
8 General Purpose I/O
This section explains software controls related to general purpose input/output (I/O) and
pin control. The FXTH87E has seven general-purpose I/O pins which are comprised of a
general use 5-bit port A and a 2-bit port B.
PTA[4:0] pins are shared with on-chip peripheral functions. PTB[1:0] pins are GPIO only
and are mutually exclusive with the LF receiver, such that PTB[1:0] pins become high
impedance when the LF is enabled (see Section 8.5 "Port B registers" for additional
details regarding mutually exclusive operations). The peripheral modules have priority
over the general purpose I/O so that when a peripheral is enabled, the general purpose
I/O functions associated with the shared pins are disabled. After reset, the shared
peripheral functions are disabled so that the pins are controlled by the general purpose
I/O. All of the general purpose I/O are configured as inputs (PTxDDn = 0) with pullup
devices disabled (PTxPEn = 0).
To avoid extra current drain from floating input pins, the user’s application software
must configure these pins so that they do not float (see Section 8.1 "Unused pin
configuration").
Reading and writing of general purpose I/O is performed through the port data registers.
The direction, either input or output, is controlled through the port data direction registers.
The general purpose I/O port function for an individual pin is illustrated in the block
diagram in Figure 13.
FXTH87ERM
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© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
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