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F87EHHD 参数 Datasheet PDF下载

F87EHHD图片预览
型号: F87EHHD
PDF下载: 下载PDF文件 查看货源
内容描述: [FXTH87E, Family of Tire Pressure Monitor Sensors]
分类和应用:
文件页数/大小: 183 页 / 1700 K
品牌: NXP [ NXP ]
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NXP Semiconductors  
FXTH87E  
FXTH87E, Family of Tire Pressure Monitor Sensors  
Table 122.ꢀLFCTRLE register field description  
Field  
Description  
7-3  
Reserved bits — Not for user access.  
Reserved  
LOGAMP AZ Sequencer Control — Control bits for AZ and trim within the LOGAMP.  
X00 Nominal AZ sequence — recommended setting  
X01 Short amp output release, max delay with Rects  
X10 Short amp output release, max delay with Amp input  
X11 All short, max delay with end of AZ  
2-0  
AZSC  
0XX Nominal sensitivity trim — recommended setting  
1XX Sensitivities shifted by — 4 trim steps  
14.17.8 LFR control register D (LFCTRLD, LPAGE = 1)  
The LFCTRLD register contains two control bits for the LF detector and decoder. It is  
only accessible when the LPAGE bit is set.  
Table 123.ꢀLFR control register D (LFCTRLD, LPAGE = 1) (address $0022)  
Bit  
R
7
6
5
4
3
2
ONMODE  
0
1
0
DEQS  
AVFOF[1:0]  
AZDC[1:0]  
CHK125[1:0]  
W
Reset  
0
0
0
0
0
0
0
= Reserved  
Table 124.ꢀLFCTRLD register field descriptions  
Field  
Description  
SUM AZ release delay — Control the delay between falling edge of SUM d_az_en input and falling edge of  
internal AZ control line.  
00ꢀNo delay  
7-6  
01ꢀNo delay  
AVFOF[1:0]  
10ꢀOne-half of 125 kHz clock period delay — recommended setting  
11ꢀOne and one-half of 125 kHz clock periods delay  
DeQing status register — This read-only status bit allows the reading of the effective activation of the  
DeQing System.  
5
0ꢀDeQing system not activated  
1ꢀDeQing system activated  
DEQS  
AZ Digital Control of AZ triggering — In data receive mode, this bits control the triggering of AZ sequence  
with respect to both LFCPTAZ value (ref. LFCTRLB register) and the state of the demodulation input data  
state.  
00ꢀAZ starts after LFCPTAZ numbers of input data edges.  
4-3  
01ꢀZ starts randomly adding –1, 0 or 1 to LFCPTAZ value between each AZ.  
10ꢀAZ starts after LFCPTAZ numbers of input data edges and when the input data (d_data) state is 0.  
AZDC[1:0]  
11ꢀAZ starts after LFCPTAZ numbers of input data edges and when the input data (d_data) state is 1 —  
recommended setting.  
FXTH87ERM  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2019. All rights reserved.  
Reference manual  
Rev. 5.0 — 4 February 2019  
130 / 183  
 
 
 
 
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