NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Field
Description
LF Receive Data Overflow Flag — In data receive mode, this read-only status flag is set when a complete
byte of data has been received and written into the LFDATA register, but the previously received byte was
not read from LFDATA register yet. This indicates that the MCU has lost the previously received data byte.
In carrier detect mode, this read-only status flag is not used and remains cleared. No separate interrupt
is generated by this specific flag bit because the LFDRF flag would serve that purpose. Clear LFOVF by
writing a one to the LFIAK bit. LFOVF is also cleared by reset.
3
LFOVF
0ꢀNormal operation.
1ꢀPrevious data over-written before MCU read it.
LF Receive Data EOM Flag — In data receive mode, this read-only status flag is set when a complete
byte of data has been received and written into the LFDATA register and an end-of-message Manchester
encoding error occurs. In carrier detect mode, this read-only status flag is not used and remains clear. No
interrupt is generated by this flag bit because the LFERF flag would serve that purpose. Clear LFEOMF by
writing a one to the LFIAK bit. LFEOMF is also cleared by reset.
2
LFEOMF
0ꢀNo EOM detected.
1ꢀEOM detected.
Low Power Sniff Mode — This bit used to activate the low power consumption during SNIFF mode. It saves
approximately 1 μA with a trade-off of an additional 200 μs in transition from carrier to data mode. LPSM is
set by reset.
1
LPSM
0ꢀLow time transition from carrier to data mode
1ꢀLow consumption during sniff mode
LF Interrupt Acknowledge — Writing a one to the LFIAK bit clears the LFDRF, LFERF, LFCDF, LFIDF,
LFOVF and LFEOMF flag bits. When a one is written to the LFIAK, it is automatically cleared at the next
positive edge of the MCU bus clock. Then, reading the LFIAK bit is allowed but will always return zero.
Writing a zero the LFIAK bit has no effect. Reset has no effect on this bit.
0
LFIAK
0ꢀNo effect.
1ꢀClears the LFDRF, LFERF, LFCDF, LFIDF, LFOVF and LFEOMF flag bits.
14.17.6 LFR data register (LFDATA, LPAGE = 0)
The LFDATA is a read-only register that contains the most recent received data value. It
is only accessible when the LPAGE bit is clear. As data is serially received by the LFR, it
is assembled into 8-bit values. When a new complete 8-bit value is received, it is moved
into the LFDATA register, over-writing any previous value, and the LFDRF data ready
flag is set to indicate a value is available for the MCU to read. If a previous value was
ready but was not read out of the LFDATA register before a new data byte is ready, the
LFOVF overflow flag is also set to indicate this overflow condition. Writes to LFDATA
have no meaning or effect.
Table 116.ꢀLFR data register (LFDATA) when LPAGE = 0 (address $0025)
Bit
R
7
6
5
4
3
2
1
0
RXDATA[7:0]
W
Reset
0
0
0
0
0
0
0
0
= Reserved
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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