NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Field
Description
ON Behavior Mode — This read/write bit selects how an error will affect the ON time. This bit is cleared by
reset.
2
0ꢀAny error will stop the ON time.
ONMODE
1ꢀIf remaining ON time, the LFR will go back to sniff mode at any error — recommended setting.
Accurate 125 kHz Check — The bit controls the CARVAL frequency check method.
00ꢀCARVAL validates on n (2*32 μs packets), n depending on LFCDTM value — recommended setting for
Low Sensitivity mode.
1-0
01ꢀSame as 10.
CHK125[1:0]
10ꢀCARVAL validates on n (8*8 μs packet), n depending on LFCDTM value — recommended setting for
High Sensitivity mode.
11ꢀSame as 00.
Note: Setting CHK125[1:0] to either 0x01 or 0x10 increases the immunity to noise and
therefore carries the side effect of narrowing the 125 kHz carrier bandwidth tolerance.
14.17.9 LFR control register C (LFCTRLC, LPAGE = 1)
The LFCTRLC register contains control bits for the LF detector and decoder. It is only
accessible when the LPAGE bit is set.
Table 125.ꢀLFR control register C (LFCTRLC, LPAGE = 1) (address $0023)
Bit
R
7
6
5
4
3
AZEN
1
2
1
0
DEQEN
0
AMPGAIN[1:0]
FINSEL[1:0]
LOWQ[1:0]
W
Reset
1
1
0
0
0
0
Table 126.ꢀLFCTRLC register field descriptions
Field
Description
3rd Amplifier gain — These bits controls the 3rd amplifier gain.
00ꢀGain of 2 — recommended setting
01ꢀGain of 3
7-6
AMPG
AIN[1:0]
10ꢀGain of 4
11ꢀGain of 6
Final stage select — These bits select the final stage of the LOGAMP.
00ꢀContinuous time biasing — Fixed Gain 6
5-4
01ꢀContinuous time biasing — Programmable Gain — recommended setting
10ꢀ4th rectifier disabled
FINSEL[1:0]
11ꢀ4th rectifier disabled
Data AZ enable — This bit allows the AZ sequence during data frame.
0ꢀAZ during data disabled
3
AZEN
1ꢀAZ during data enabled — recommended setting
DeQing Resistor — These bits select the resistor added in parallel to the input network.
00ꢀ4 kΩ
01ꢀ2 kΩ
10ꢀ1 kΩ
11ꢀ500 Ω
2-1
LOWQ[1:0]
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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