NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
256-BIT
DATA BUFFER
RINT
RF
STATE
MACHINE
LFSR
RANDOM
GEN
MODULATION
CONTROL
RF
RF
MFO
MCU
AMP
CONTROL
REGISTERS
AND LOGIC
DX
500 kHz
FRACTIONAL-N
DIVIDER
XI
CRYSTAL
OSCILLATOR
PHASE
DETECTOR
LOW-PASS
FILTER
VCO
XO
RF
LVD
VOLT
REG
RF
AVDD
AVDD
AVSS
VREG
aaa-028030
Figure 37.ꢀRF transmitter block diagram
15.1 RF data modes
There are two modes of operation in using the RF output in either the data buffer mode
or MCU direct mode.
15.1.1 RF data buffer mode
In the RF data buffer mode the transmissions are sent by dedicated logic hardware while
the MCU can be put into a low power mode until the transmission is completed. This RF
state machine is clocked by the MFO which is enabled when the SEND bit is set and
when any of the LFR, SMI or MCU are operating.
The RF data buffer consists of a dedicated RFM state machine and a 256-bit data buffer.
The RF data buffer is loaded with whatever data pattern the user software creates. The
number of data bits to be sent is selected by the FRM[7:0] control bits. The control logic
is triggered by the SEND control bit when it is time to transmit the data which is sent to
the RF stage after being encoded as either Manchester, Bi-Phase or NRZ data according
to the method selected by the CODE[1:0] bits as described in Section 15.17 "PLL control
registers A - PLLCR[1:0], RPAGE = 0".
Before the data can be transmitted the RFM control logic enables the external crystal
oscillator and phase-locked-loop to initialize before the RF output stage can begin
transmission.
The external crystal connected to the X0 and XI pins provides the carrier frequency as
well as the data rate clock needed for the data rates associated with the OOK or FSK
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
134 / 183
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