NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
Table 117.ꢀLFDATA register field descriptions
Field
Description
7:0
Receive Data [7:0] — This is the received data from the LFR when in the data mode. All bits are read-only
and any writes to these bits will be ignored. Reading this register will clear the LFDRF.
RXDATA[7:0]
14.17.7 LFR ID registers (LFIDH:LFIDL, LPAGE = 0)
These two 8-bit read/write registers hold one of two ID values for LF messages. They are
only accessible when the LPAGE bit is clear. The type of ID checking can be selected
or disabled by using the IDSEL[1:0] bits in the LFCTL1 register. When ID checking is
enabled, the ID value received through the LFR must match the contents of the LFIDH
and/or LFIDL registers depending on the IDSEL bits or the message will be ignored and
the MCU will remain in standby mode to minimize power consumption. All these bits are
cleared by a reset.
Table 118.ꢀLFR ID low byte (LFIDL) (address $0026)
Bit
R
7
6
5
4
3
2
1
0
ID[0:7]
W
Reset
0
0
0
0
0
0
0
0
Table 119.ꢀLFR ID high byte (LFIDH) (address $0027)
Bit
R
7
6
5
4
3
2
1
0
ID[15:8]
W
Reset
0
0
0
0
0
0
0
0
Table 120.ꢀLFR ID register field description
Field
Description
ID[15:0]
ID bits 15 through 0 — These read/write bits contain bits 15 through 0 of the 16-bit ID value.
14.17.7.1 LF Control E — LFCTRLE
Table 121.ꢀLF control E (LFCTRLE) (address $0021)
Bit
R
7
6
5
4
3
2
AZSC2
0
1
AZSC1
0
0
AZSC0
0
W
Reset
0
0
0
0
0
= Reserved
FXTH87ERM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2019. All rights reserved.
Reference manual
Rev. 5.0 — 4 February 2019
129 / 183
NXP [ NXP ]
