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F87EHHD 参数 Datasheet PDF下载

F87EHHD图片预览
型号: F87EHHD
PDF下载: 下载PDF文件 查看货源
内容描述: [FXTH87E, Family of Tire Pressure Monitor Sensors]
分类和应用:
文件页数/大小: 183 页 / 1700 K
品牌: NXP [ NXP ]
 浏览型号F87EHHD的Datasheet PDF文件第128页浏览型号F87EHHD的Datasheet PDF文件第129页浏览型号F87EHHD的Datasheet PDF文件第130页浏览型号F87EHHD的Datasheet PDF文件第131页浏览型号F87EHHD的Datasheet PDF文件第133页浏览型号F87EHHD的Datasheet PDF文件第134页浏览型号F87EHHD的Datasheet PDF文件第135页浏览型号F87EHHD的Datasheet PDF文件第136页  
NXP Semiconductors  
FXTH87E  
FXTH87E, Family of Tire Pressure Monitor Sensors  
Field  
Description  
DeQing System enable — The bit controls the DeQing system.  
0ꢀDeQing disabled.  
0
DEQEN  
1ꢀDeQing enabled.  
14.17.10 LFR control register B (LFCTRLB, LPAGE = 1)  
The LFCTRLB register contains control bits for the LF detector and decoder. It is only  
accessible when the LPAGE bit is set.  
Table 127.ꢀLFR control register B (LFCTRLB, LPAGE = 1) (address $0024)  
Bit  
R
7
6
5
LFFAF  
0
4
LFCAF  
0
3
LFPOL  
0
2
1
0
HYST[1:0]  
LCPTAZ[2:0]  
0
W
Reset  
1
1
1
0
Table 128.ꢀLFCTRLB register field descriptions  
Field  
Description  
Control slicer hysteresis  
00ꢀ20 mV hysteresis  
01ꢀ40 mV hysteresis  
10ꢀ50 mV hysteresis  
7-6  
HYST[1:0]  
11ꢀ30 mV hysteresis — recommended setting  
Average filter bi-phase filtering control — Activates bi-phase filtering and control offset value  
00ꢀStandard low pass filtering activated — recommended setting  
01ꢀStandard low pass filtering activated  
5-4  
LFFAF;  
LFCAF  
10ꢀBi-phase filtering activated — Low offset from input signal low level  
11ꢀBi-phase filtering activated — High offset from input signal low level  
LF Manchester Polarity Select — This read/write bit selects the polarity of the transition in the middle of the  
bit time. The LFPOL is not used in Carrier mode. Reset clears LFPOL bit.  
3
0ꢀZero is falling edge in middle of a bit time, one is a rising edge in the middle of bit time.  
1ꢀZero is rising edge in middle of a bit time, one is a falling edge in the middle of bit time.  
LFPOL  
2-0  
LF auto-zero counter — Applications to set these bits to 0x06 for proper LF operation. These bits tune the  
minimum number of data edges between two auto-zero requests during a data frame.  
LFCPT  
AZ[2:0]  
14.17.11 LFR control register A (LFCTRLA, LPAGE = 1)  
The LFCTRLA register contains control bits for the LF detector and factory test selects. It  
is only accessible when the LPAGE bit is set.  
Table 129.ꢀLFR control register A (LFCTRLA, LPAGE = 1) (address $0025)  
Bit  
R
7
6
5
4
3
2
1
0
LFCC[3:0]  
W
Reset  
0
0
0
0
0
0
0
0
FXTH87ERM  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2019. All rights reserved.  
Reference manual  
Rev. 5.0 — 4 February 2019  
132 / 183  
 
 
 
 
 
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