NXP Semiconductors
FXTH87E
FXTH87E, Family of Tire Pressure Monitor Sensors
14.17.4 LFR control register 4 (LFCTL4)
LFCTL4 contains local interrupt enable control bits. The provided I-interrupts are not
globally masked by the I bit in the CPU’s CCR, setting one or more of these interrupt
enable control bits will cause a CPU interrupt to be requested whenever the flag bit
associated with the corresponding LFR interrupt source becomes set. It is good practice
to clear any flag bits in the LFS register before setting interrupt enable bits in this register
in order to avoid an immediate interrupt request.
Table 112.ꢀLFR control register 4 (LFCTL4) (address $0023)
Bit
R
7
LFDRIE
0
6
LFERIE
0
5
LFCDIE
0
4
LFIDIE
0
3
DECEN
1
2
VALEN
1
1
0
TIMOUT[1:0]
W
Reset
0
0
Table 113.ꢀLFCTL4 register field descriptions
Field
Description
LFR Data Register Full Interrupt Enable — This read/write bit enables interrupts to be requested when the
LFR data register is full. Reset clears LFDRIE.
7
0ꢀLFDRF interrupts disabled. Use software polling.
LFDRIE
1ꢀLFR Data Register Full interrupts are enabled. If LFDRIE is set, then an interrupt is requested when
LFDRF = 1.
LFR Error Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR detects
an error in reception of a non-Manchester encoded bit time following the SYNC time. Reset clears LFERIE.
6
0ꢀLFERF interrupts disabled. Use software polling.
LFERIE
1ꢀLFERF interrupts are enabled. If LFERIE is set, then an interrupt is requested when LFERF = 1.
LFR Carrier Detect Interrupt Enable — This read/write bit enables the LFCDF interrupt when the LFR
detects the number of samples with an LF signal defined by the LFCDTM bits in the LFCTL3 register. The
LFCDIE is ignored when the LFR is operating in the data mode (CARMOD = 0), except when DECEN is
cleared. Reset clears LFCDIE.
5
LFCDIE
0ꢀLFCDF interrupts disabled.
1ꢀLFR LFCDF interrupts are enabled. If LFCDIE is set, then an interrupt is requested when LFCDF = 1.
LFR ID Detect Interrupt Enable — This read/write bit enables interrupts to be requested when the LFR
detects a match to the ID code selected in the LFIDH:L registers. Reset clears LFIDIE.
4
0ꢀLFIDF interrupts disabled.
LFIDIE
1ꢀLFIDF interrupts are enabled. If LFIDIE is set, then an interrupt is requested when LFIDF = 1.
LF Digital Decode Enable — This read/write bit enables the data processing by the digital decoder. When
disabled, the frame format (Manchester, data-rate, SYNC, data) is not checked. There is no more error flag
assertion (data, error, ID). The MCU should then poll the LFDO bit to extract from the analog detector the bit
stream. Reset sets the DECEN bit.
3
DECEN
0ꢀDigital decoder is disabled.
1ꢀDigital decoder is enabled.
LF Validation Enable — This read/write bit enables the carrier validation process. Reset sets this bit.
0ꢀCarrier Validation disabled.
2
VALEN
1ꢀCarrier Validation enabled.
FXTH87ERM
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Reference manual
Rev. 5.0 — 4 February 2019
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