Nano100(A)
5.16.2 Features
Supports two I2C channels and both of them can acts as Master or Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
One built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
Programmable clock divider allows versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition ( Two slave addresses with mask option)
Mar 31, 2015
Page 71 of 95
Revision V1.00
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