Nano100(A)
byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte.
A transition on the SDA line while SCL is high is interpreted as a command (START or STOP).
Each bit is sampled during the high period of SCL; therefore, the SDA line may be changed only
during the low period of SCL and must be held stable during the high period of SCL.
The controller’s on-chip I2C logic provides the serial interface that meets the I2C bus standard
mode specification. The I2C controller handles byte transfers autonomously. Pull up resistor is
needed for I2C operation as these are open drain pins.
The I2C controller is equipped with two slave address registers. The contents of the registers are
irrelevant when I2C is in Master mode. In the Slave mode, the seven most significant bits must be
loaded with the user’s own slave address. The I2C hardware will react if the contents of I2CADDR
are matched with the received slave address.
This controller supports the “General Call (GC)” function. If the GCALL (I2CSADDR[0]) bit is set
this controller will respond to General Call address (00H). Clear GC bit to disable general call
function. When GCALL bit is set and the I2C is in Slave mode, it can receive the general call
address which is equal to 00H after master sends general call address to the I2C bus, then it will
follow status of GC mode. If it is in Master mode, the ACK bit must be cleared when it sends
general call address of 00H to the I2C bus.
The I2C-bus controller supports multiple address recognition with two address mask register.
When the bit in the address mask register is set to one, it means the received corresponding
address bit is don’t-care. If the bit is set to 0, that means the received corresponding register bit
should be exact the same as address register.
Mar 31, 2015
Page 70 of 95
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