Nano100(A)
5.19 USB
5.19.1 Overview
The USB controller is a USB 2.0 full-speed device controller. It is compliant with USB 2.0 full
speed device specification and supports control/bulk/interrupt/isochronous transfer types.
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There is an internal 512-byte SRAM as data buffer in this controller. For IN token or OUT token
transfer, it is necessary to write data to SRAM or read data from SRAM through the APB
interface. Users need to allocate the effective starting address of SRAM for each endpoint buffer
through “buffer segmentation register (BUFSEG)”.
This device controller contains 6 configurable endpoints. Each endpoint can be configured as IN
or OUT endpoint. The function address of the device and endpoint number in each endpoint shall
be configured properly in advance for receiving or transmitting a data packet correctly. The
transmitting/receiving length in each endpoint is defined in maximum payload register (MXPLD)
and the handshakes between Host and Device are also handled by it.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, like IN ACK, OUT ACK etc, and BUS events, like suspend
and resume, etc. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of events
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables the DRVSE0 bit (USB_DRVSE0), the
USB controller will force USB_DP and USB_DM to level low and USB device function is disabled
(disconnected). After disable the DRVSE0 bit, host will enumerate the USB device again.
Reference: Universal Serial Bus Specification Revision 2.0
5.19.2 Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature listing of this USB.
Compliant with USB 2.0 Full-Speed specification.
Provide 1 interrupt vector with 4 different interrupt events (WAKEUP, FLDET, USB
and BUS).
Supports Control/Bulk/Interrupt/Isochronous transfer type.
Supports suspend function when no bus activity existing for 3 ms.
Provide 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer types
512-byte SRAM buffer inside
Provide remote wake-up capability.
Mar 31, 2015
Page 74 of 95
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