Nano100(A)
5.17 SPI
5.17.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol.
Devices communicate in Master/Slave mode with 4-wire bi-direction interface. It is used to
perform a serial-to-parallel conversion on data received from a peripheral device, and a parallel-
to-serial conversion on data transmitted to a peripheral device. The SPI controller can be
configured as a master or a slave device.
The SPI controller supports wake-up function. When this chip stays in power-down mode, it can
be waked up chip by off-chip device.
This controller supports variable serial clock for special application and 2 data channel transfer
mode to connect 2 off-chip slave devices. The SPI controller also supports PDMA function to
access the data buffer.
5.17.2 Features
Up to two sets of SPI controllers
Supports Master (max. 16 MHz) or Slave (max. 6 MHz) mode operation
Supports 1 bit data channel and 2 bit data channel transfer mode
Configurable bit length of a transaction from 8 to 32 bits and configurable transaction
number up to 2 of a transfer in burst mode, so the maximum bit length is 64 bits for
each data transfer in burst mode
Supports MSB first or LSB first transfer sequence
Two slave select lines supported in Master mode
Configurable byte or word suspend mode
Supports byte re-ordering function
Supports variable serial clock in Master mode
Provide Dual FIFO buffers
Supports wake-up function
Supports PDMA transfer
Supports 3-wires, no slave select signal, bi-direction interface
Mar 31, 2015
Page 72 of 95
Revision V1.00
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