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NANO127SC1AN 参数 Datasheet PDF下载

NANO127SC1AN图片预览
型号: NANO127SC1AN
PDF下载: 下载PDF文件 查看货源
内容描述: [ARM® Cortex®-M 32-bit Microcontroller]
分类和应用: 微控制器
文件页数/大小: 95 页 / 2021 K
品牌: NUVOTON [ NUVOTON ]
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Nano100(A)  
5.13 RTC  
5.13.1 Overview  
Real Time Clock (RTC) unit provides user the real time and calendar message. The Clock Source  
of RTC is from an external 32.768 kHz crystal connected at pins X32I and X32O (reference to pin  
Description) or from an external 32.768 kHz oscillator output fed at pin X32I. The RTC unit  
provides the time message (second, minute, hour) in Time Loading Register (TLR) as well as  
calendar message (day, month, year) in Calendar Loading Register (CLR). The data message is  
expressed in BCD format. This unit offers alarm function that user can preset the alarm time in  
Time Alarm Register (TAR) and alarm calendar in Calendar Alarm Register (CAR).  
The RTC unit supports periodic Time Tick and Alarm Match interrupts. The periodic interrupt has  
8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by TTR  
(TTR[2:0]). When RTC counter in TLR and CLR is equal to alarm setting time registers TAR and  
CAR, the alarm interrupt flag (AIS(RTC_RIIR[0])) is set and the alarm interrupt is requested if the  
alarm interrupt is enabled (AIER(RTC_RIER[0])=1). The RTC Time Tick (if wake-up CPU function  
is enabled, (TWKE(RTC_TTR[3])) high)) and Alarm Match can cause CPU wake-up from idle or  
Power-down mode.  
5.13.2 Features  
There is a time counter (second, minute, hour) and calendar counter (day, month,  
year) for user to check the time.  
Alarm register (second, minute, hour, day, month, year).  
12-hour or 24-hour mode is selectable.  
Leap year compensation automatically.  
Day of week counter.  
Frequency compensate register (FCR).  
All time and calendar message is expressed in BCD code.  
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,  
1/4, 1/2 and 1 second.  
Supports RTC Time Tick and Alarm Match interrupt  
Supports wake-up CPU from power-down mode.  
Supports 80 bytes spare registers and a snoop pin to clear the content of these spare  
registers.  
Mar 31, 2015  
Page 67 of 95  
Revision V1.00  
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