Nano100(A)
5.15 Smart Card Host Interface (SC)
5.15.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
5.15.2 Features
ISO-7816-3 T = 0, T = 1 compliant.
EMV2000 compliant
Up to two ISO-7816-3 ports
Separates receive/transmit 4 byte entry FIFO for data payloads.
Programmable transmission clock frequency.
Programmable receiver buffer trigger level.
Programmable guard time selection (11 ETU ~ 267 ETU).
A 24-bit and two 8 bit timers for Answer to Request (ATR) and waiting times
processing.
Supports auto inverse convention function.
Supports transmitter and receiver error retry and error number limitation function.
Supports hardware activation sequence process.
Supports hardware warm reset sequence process.
Supports hardware deactivation sequence process.
Supports hardware auto deactivation sequence when detected the card removal.
Supports UART mode
Half duplex, asynchronous communications.
Separates receiving / transmitting 4 bytes entry FIFO for data payloads.
Supports programmable baud rate generator for each channel.
Supports programmable receiver buffer trigger level.
Programmable transmitting data delay time between the last stop bit leaving the
TX-FIFO and the de-assertion by setting SC_EGTR register.
Programmable even, odd or no parity bit generation and detection.
Programmable stop bit, 1 or 2 stop bit generation.
5.16 I2C
5.16.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously. Serial, 8-bit oriented bi-directional data transfers can be made up to 1
Mbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
Mar 31, 2015
Page 69 of 95
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