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M25PE80-VMN6P 参数 Datasheet PDF下载

M25PE80-VMN6P图片预览
型号: M25PE80-VMN6P
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存内存集成电路
文件页数/大小: 66 页 / 1387 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25PE80  
Instructions  
6.17  
Release from deep power-down (RDP)  
Once the device has entered the deep power-down mode, all instructions are ignored  
except the release from deep power-down (RDP) instruction. Executing this instruction  
takes the device out of the deep power-down mode.  
The release from deep power-down (RDP) instruction is entered by driving Chip Select (S)  
Low, followed by the instruction code on serial data input (D). Chip Select (S) must be driven  
Low for the entire duration of the sequence.  
The instruction sequence is shown in Figure 23.  
The release from deep power-down (RDP) instruction is terminated by driving Chip Select  
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven  
Low, cause the instruction to be rejected, and not executed.  
After Chip Select (S) has been driven High, followed by a delay, t  
, the device is put in the  
RDP  
standby mode. Chip Select (S) must remain High at least until this period is over. The device  
waits to be selected, so that it can receive, decode and execute instructions.  
Any release from deep power-down (RDP) instruction, while an erase, program or write  
cycle is in progress, is rejected without having any effects on the cycle that is in progress.  
Figure 23. Release from deep power-down (RDP) instruction sequence  
S
tRDP  
0
1
2
3
4
5
6
7
C
D
Instruction  
High Impedance  
Q
Deep power-down mode  
Standby mode  
AI06807  
45/66  
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