M25PE80
Instructions
6.13
Subsector erase (SSE)
Note:
The subsector erase (SSE) instruction is decoded only in the M25PE80 in the T9HX
process (see Important note on page 6).
The subsector erase (SSE) instruction sets to ‘1’ (FFh) all bits inside the chosen subsector.
Before it can be accepted, a write enable (WREN) instruction must previously have been
executed. After the write enable (WREN) instruction has been decoded, the device sets the
write enable latch (WEL).
The subsector erase (SE) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, and three address bytes on serial data input (D). Any address inside
the subsector (see Table 5) is a valid address for the subsector erase (SE) instruction. Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 20.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the subsector erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed subsector erase cycle (whose duration is t
) is
SSE
initiated. While the subsector erase cycle is in progress, the status register may be read to
check the value of the write in progress (WIP) bit. The write in progress (WIP) bit is 1 during
the self-timed subsector erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the write enable latch (WEL) bit is reset.
A subsector erase (SSE) instruction applied to a subsector that contains a page that is
hardware or software protected is not executed.
Any subsector erase (SSE) instruction, while an erase, program or write cycle is in progress,
is rejected without having any effects on the cycle that is in progress.
If Reset (Reset) is driven Low while a subsector erase (SSE) cycle is in progress, the
subsector erase cycle is interrupted and data may not be erased correctly (see Table 15:
Device status after a Reset Low pulse). On Reset going Low, the device enters the reset
mode and a time of t
is then required before the device can be re-selected by driving
RHSL
Chip Select (S) Low. For the value of t
see Table 26: Timings after a Reset Low pulse in
RHSL
Section 11: DC and AC parameters.
Figure 19. Subsector erase (SSE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24-bit address
2
0
1
23 22
MSB
AI12356
1. Address bits A23 to A20 are don’t care.
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NUMONYX [ NUMONYX B.V ]
