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M25PE80-VMN6P 参数 Datasheet PDF下载

M25PE80-VMN6P图片预览
型号: M25PE80-VMN6P
PDF下载: 下载PDF文件 查看货源
内容描述: 8兆位,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [8-Mbit, page-erasable serial flash memory with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存内存集成电路
文件页数/大小: 66 页 / 1387 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25PE80  
Instructions  
6.15  
Bulk erase (BE)  
The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write  
enable (WREN) instruction must previously have been executed. After the write enable  
(WREN) instruction has been decoded, the device sets the write enable latch (WEL).  
The bulk erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the  
instruction code on serial data input (D). Chip Select (S) must be driven Low for the entire  
duration of the sequence.  
The instruction sequence is shown in Figure 21.  
Chip Select (S) must be driven High after the eighth bit of the instruction code has been  
latched in, otherwise the bulk erase instruction is not executed. As soon as Chip Select (S)  
is driven High, the self-timed bulk erase cycle (whose duration is t ) is initiated. While the  
BE  
bulk erase cycle is in progress, the status register may be read to check the value of the  
write in progress (WIP) bit. The write in progress (WIP) bit is 1 during the self-timed bulk  
erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is  
completed, the write enable latch (WEL) bit is reset.  
Any bulk erase (BE) instruction, while an erase, program or write cycle is in progress, is  
rejected without having any effects on the cycle that is in progress. A bulk erase (BE)  
instruction is ignored if at least one sector or subsector is write-protected (Hardware or  
software protection).  
If Reset (Reset) is driven Low while a bulk erase (BE) cycle is in progress, the bulk erase  
cycle is interrupted and data may not be erased correctly (see Table 15: Device status after  
a Reset Low pulse). On Reset going Low, the device enters the reset mode and a time of  
t
is then required before the device can be re-selected by driving Chip Select (S) Low.  
RHSL  
For the value of t  
see Table 26: Timings after a Reset Low pulse in Section 11: DC and  
RHSL  
AC parameters.  
Figure 21. Bulk erase (BE) instruction sequence  
S
0
1
2
3
4
5
6
7
C
D
Instruction  
AI03752D  
43/66  
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