PSMN102-200Y
Nexperia
N-channel TrenchMOS SiliconMAX standard level FET
2. Pinning information
Table 2.
Pinning information
Symbol Description
Pin
1
Simplified outline
Graphic symbol
S
S
S
G
D
source
source
source
gate
mb
D
S
2
3
G
4
mbb076
mb
mounting base; connected to
drain
1
2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Type number
Package
Name
Description
Version
PSMN102-200Y
LFPAK
plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDS
Parameter
Conditions
Min
Max
200
200
20
Unit
V
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
Tj ≥ 25 °C; Tj ≤ 150 °C
Tj ≥ 25 °C; Tj ≤ 150 °C; RGS = 20 kΩ
-
VDGR
VGS
-
V
-20
-
V
ID
VGS = 10 V; Tmb = 25 °C; see Figure 1;
see Figure 3
21.5
A
VGS = 10 V; Tmb = 100 °C; see Figure 1
-
-
13.6
65
A
A
IDM
peak drain current
pulsed; tp ≤ 10 µs; Tmb = 25 °C;
see Figure 3
Ptot
Tstg
Tj
total power dissipation
storage temperature
junction temperature
Tmb = 25 °C; see Figure 2
-
113
150
150
W
-55
-55
°C
°C
Source-drain diode
IS
source current
peak source current
Tmb = 25 °C
-
-
52
A
A
ISM
pulsed; tp ≤ 10 µs; Tmb = 25 °C
208
Avalanche ruggedness
EDS(AL)S
non-repetitive drain-source
avalanche energy
VGS = 10 V; Tj(init) = 25 °C; ID = 10.8 A;
Vsup ≤ 200 V; unclamped; tp = 0.14 ms;
RGS = 50 Ω
-
202
mJ
PSMN102-200Y
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 16 March 2011
2 of 13
NEXPERIA [ Nexperia ]
