Nexperia
PSMN0R9-25YLD
N-channel 25 V, 0.85 mΩ, 300 A logic level MOSFET in LFPAK56 using
NextPowerS3 Technology
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
ΔVGS(th)/ΔT
gate-source threshold 25 °C ≤ Tj ≤ 175 °C
voltage variation with
-
-5.1
-
mV/K
temperature
IDSS
drain leakage current
gate leakage current
VDS = 20 V; VGS = 0 V; Tj = 25 °C
-
-
-
-
-
-
1
µA
µA
nA
nA
mΩ
VDS = 20 V; VGS = 0 V; Tj = 125 °C
VGS = 20 V; VDS = 0 V; Tj = 25 °C
VGS = -20 V; VDS = 0 V; Tj = 25 °C
30
-
IGSS
-
100
100
1.2
-
RDSon
drain-source on-state
resistance
VGS = 4.5 V; ID = 25 A; Tj = 25 °C;
Fig. 10
0.96
VGS = 4.5 V; ID = 25 A; Tj = 175 °C;
Fig. 10; Fig. 11
-
-
-
-
-
2.04
0.85
1.45
-
mΩ
mΩ
mΩ
Ω
VGS = 10 V; ID = 25 A; Tj = 25 °C;
Fig. 10
0.72
-
VGS = 10 V; ID = 25 A; Tj = 175 °C;
Fig. 10; Fig. 11
RG
gate resistance
f = 1 MHz
1.16
Dynamic characteristics
QG(tot)
total gate charge
ID = 25 A; VDS = 12 V; VGS = 10 V;
Fig. 12; Fig. 13
-
-
89.8
41.5
-
-
nC
nC
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Fig. 12; Fig. 13
ID = 0 A; VDS = 0 V; VGS = 0 V
-
-
-
47.2
15.8
9.7
-
-
-
nC
nC
nC
QGS
gate-source charge
ID = 25 A; VDS = 12 V; VGS = 4.5 V;
Fig. 12; Fig. 13
QGS(th)
pre-threshold gate-
source charge
QGS(th-pl)
post-threshold gate-
source charge
-
6.1
-
nC
QGD
gate-drain charge
-
-
9.9
2.7
-
-
nC
V
VGS(pl)
gate-source plateau
voltage
ID = 25 A; VDS = 12 V; Fig. 12; Fig. 13
Ciss
Coss
Crss
input capacitance
output capacitance
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; Fig. 14
-
-
-
6721
2390
418
-
-
-
pF
pF
pF
reverse transfer
capacitance
td(on)
tr
td(off)
tf
turn-on delay time
rise time
VDS = 12 V; RL = 0.6 Ω; VGS = 4.5 V;
RG(ext) = 5 Ω
-
-
-
-
-
37.9
42
-
-
-
-
-
ns
ns
ns
ns
nC
turn-off delay time
fall time
39.2
27.9
Qoss
output charge
VGS = 0 V; VDS = 12 V; f = 1 MHz
All information provided in this document is subject to legal disclaimers.
27 April 2016
44
©
PSMN0R9-25YLD
Nexperia B.V. 2017. All rights reserved
Product data sheet
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