CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.5 Address Map
The address maps of the CPU memory space and PCI bus I/O or memory space are shown below.
Figure 3-3. CPU Memory Space/PCI Bus I/O Space Address Map
CPU memory space
PCI bus I/O space
FFFF FFFFH
IO_BASE[31:16] + FFFFH
IO_BASE[31:16] + 0000H
FFFFH
0000H
PCI I/O area
64 KB
PCI bus I/O space
64 KB
I_CPU_CS1_B area
0000 0000H
Figure 3-4. CPU Memory Space/PCI Bus Memory Space Address Map
CPU memory space
PCI bus memory space
FFFF FFFFH
M_BASE[31:16] + FFFFFH
M_BASE[31:16] + 00000H
FFFFFH
00000H
PCI memory area
1 MB
PCI memory space
1 MB
I_CPU_CS2_B area
S_BASE[31:16] + S_RANGE[31:16] + FFFFH
S_BASE[31:16] + S_RANGE[31:16] + 0000H
O_SD_CS_B output
when accessing from
PCI host bridge
Main memory
(SDRAM) area
Main memory space
0000 0000H
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Application Note U17121EJ1V1AN
NEC [ NEC ]
