CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.10 SDRAM_CTL register
After reset: 00070230H
31
R/W
Offset address: 48H
CYCLE_LATENCY
24 23
16 15
13 12 11 10
9
8
7
0
6
0
5
4
3
0
2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit Name
R/W
Function
CYCLE_LATENCY
R/W Sets the latency for successive main memory (SDRAM) accesses from the PCI device.
A latency of up to 7,650 ns can be set.
00H: No latency
01H: 1 PCI clock (30 ns)
:
FFH: 255 PCI clocks (7,650 ns)
BUS_SIZE
R/W Sets the bit width of the data bus.
0: 16-bit width
1: 32-bit width
CAS_LATENCY
R/W Sets the CAS latency.
00: Setting prohibited
01: 1
10: 2
11: 3
WAIT_STATE
R/W Sets the wait interval of ACT → CMD, PRE → ACT, and CMD → ACT.
00: Setting prohibited
01: 1 clock
10: 2 clocks
11: 3 clocks
COLUMN_SIZE
R/W Sets the bit width of the column address.
00: 8-bit width
01: 9-bit width
10: 10-bit width
11: 11-bit width
42
Application Note U17121EJ1V1AN
NEC [ NEC ]
