CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
3.4.7 PCI_ERR_ADD register
The PCI_ERR_ADD register retains the PCI bus address when the following errors occur.
• System error (SERR# reception)
• Parity error (PERR# reception)
• Master abort
• Target abort
When the PCI_ERR_ADD register is read, all the bits are cleared. Once an error occurs and a value is set to the
PCI_ERR_ADD register, the first value is retained until read access is performed or a new error occurs and the value
is updated.
This function is used only for debugging and is not used in normal operation.
After reset: 00000000H
31
R
Offset address: 1CH
0
ERR_ADR
Bit Name
R/W
Function
Retains the address when a PCI bus error occurs.
ERR_ADR
R
40
Application Note U17121EJ1V1AN
NEC [ NEC ]
