CHAPTER 3 SPECIFICATIONS OF PCI HOST BRIDGE MACRO
Figure 3-8. Hold Request/Hold Acknowledge
I_SDCLK
O_HOLDREQ_B
I_HOLDACK_B
EN_SD_CTL
SDRAM control
signal output
Figure 3-9. Main Memory (SDRAM) Write Access (8-Burst)
I_SDCLK
O_HOLDREQ_B
I_HOLDACK_B
O_SD_CS_B
O_SD_RAS_B
O_SD_CAS_B
O_SD_WR_B
O_SD_ADR1 to
O_SD_ADR25
RA
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7
WD0 WD1 WD2 WD3 WD4 WD5 WD6 WD7
O_SD_DATA0 to
O_SD_DATA31
O_SD_DQM_B0 to
O_SD_DQM_B3
1111
1111
Remark SDRAM_CTL register WAIT_STATE field = 10, CAS_LATENCY field = 10
48
Application Note U17121EJ1V1AN
NEC [ NEC ]
