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UPD703100AGJ-40-8EU 参数 Datasheet PDF下载

UPD703100AGJ-40-8EU图片预览
型号: UPD703100AGJ-40-8EU
PDF下载: 下载PDF文件 查看货源
内容描述: V850E / MS1TM 16分之32位单芯片微控制器 [V850E/MS1TM 32/16-BIT SINGLE-CHIP MICROCONTROLLERS]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 132 页 / 1155 K
品牌: NEC [ NEC ]
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µPD703100A-33, 703100A-40, 703101A-33, 703102A-33  
DC Characteristics (TA = –40 to +70°C ... µPD703100A-40,  
TA = –40 to +85°C ... µPD703100A-33, µPD703101A-33, µPD703102A-33,  
VDD = HVDD = CVDD = 3.0 to 3.6 V, = VSS = 0 V)  
Parameter  
Symbol  
VIH  
Condition  
Except Note 1  
MIN.  
0.65HVDD  
0.8HVDD  
0.5  
TYP.  
MAX.  
Unit  
V
Input voltage, high  
HVDD + 0.3  
HVDD + 0.3  
0.2HVDD  
Note 1  
V
Input voltage, low  
VIL  
VXH  
VXL  
Except Note 1 and Note 2  
V
Note 1  
0.5  
0.15HVDD  
VDD + 0.3  
VDD + 0.3  
0.15VDD  
V
Clock input voltage, high  
Clock input voltage, low  
X1 pin  
Direct mode  
PLL mode  
Direct mode  
PLL mode  
0.8VDD  
0.8VDD  
0.3  
V
V
X1 pin  
V
0.3  
0.15VDD  
V
Schmitt-triggered input  
threshold voltage  
HVT+  
Note 1, rising edge  
Note 1, falling edge  
Note 1  
2.0  
1.0  
V
HVT  
V
Schmitt-triggered input  
hysteresis width  
HVT+  
0.3  
V
–HVT  
Output voltage, high  
VOH  
IOH = 1.0 mA  
0.8HVDD  
V
Output voltage, low  
VOL  
ILIH  
IOL = 2.5 mA  
0.15HVDD  
10  
V
Input leakage current, high  
Input leakage current, low  
Output leakage current, high  
Output leakage current, low  
Except V  
Except V  
I = HVDD or Note 2  
I = 0 V or Note 2  
µA  
µA  
µA  
µA  
ILIL  
10  
ILOH  
ILOL  
VO = HVDD  
VO = 0 V  
10  
10  
Notes 1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,  
P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to  
P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,  
P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,  
P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,  
P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2,  
RESET  
2. When the P70/ANI0 to P77/ANI7 pins are used as analog input.  
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = CVDD = HVDD = 3.3 V.  
2. Direct mode:  
fX = 2 to 40 MHz (µPD703100A-40)  
fX = 2 to 33 MHz (µPD703100A-33)  
fX = 10 to 33 MHz (µPD703101A-33, 703102A-33)  
PLL mode:  
fX = 2 to 40 MHz (µPD703100A-40)  
fX = 2 to 33 MHz (µPD703100A-33)  
fX = 20 to 33 MHz (µPD703101A-33, 703102A-33)  
72  
Preliminary Data Sheet U14168EJ2V0DS00  
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