µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3)
Parameter
Symbol
Condition
Unit
ns
MIN.
(1.5 + wRH + w) T – 10
(1 + wRH + w) T – 10
0
MAX.
CAS ↓ delay time from DMAAKm ↓
CAS ↓ delay time from IORD ↓
IORD ↑ delay time from WE ↑
<105>
tDDACS
tDRDCS
tDWERD
<106>
<107>
ns
wF = 0
wF = 1
ns
T – 10
ns
Remarks 1. T = tCYK
2. w: the number of waits due to WAIT.
3. wRH: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4. wF: the number of waits that are inserted for a source-side access during a DMA flyby transfer.
5. m = 0 to 3
114
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
