µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
Symbol
<24>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
tSWK
tHKW
tWRDL
tWRDH
tDARD
tDRDA
tASR
10
2
<25>
<32>
<33>
<34>
<35>
<56>
<57>
<58>
<59>
<60>
(2 + wRH + wDA + wF + w) T – 10
T – 5
IORD high-level width
IORD ↑ delay time from address, CSn
Address delay time from IORD ↑
Row address setup time
0.5T – 5
(0.5 + i) T – 5
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
Row address hold time
tRAH
Column address setup time
Column address hold time
Read/write cycle time
tASC
tCAH
(1.5 + wDA + wF) T – 10
tRC
(3 + wRP + wRH + wDA + wF + w)
T – 10
RAS precharge time
<61>
<63>
<64>
<65>
<66>
<67>
<71>
<76>
<77>
<81>
<82>
<83>
<85>
<88>
<89>
<92>
<94>
<101>
<102>
tRP
tRSH
tRAL
tCAS
tCRP
tCSH
tCPN
tRAD
tRCD
tCP
(0.5 + wRP) T – 5
(1.5 + wDA + wF) T – 10
(2 + wCP + wDA + wF + w) T – 10
(1 + wDA + wF) T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RAS hold time
Column address read time for RAS
CAS pulse width
CAS-RAS precharge time
CAS hold time
(1 + wRP) T – 10
(2 + wRH + wDA + wF + w) T – 10
(2 + wRP + wRH + w) T – 5
(0.5 + wRH) T – 10
CAS precharge time
RAS column address delay time
RAS-CAS delay time
(1 + wRH + w) T – 10
CAS precharge time
(0.5 + wCP + w) T – 5
High-speed page mode cycle time
RAS hold time for CAS precharge
WE hold time (from CAS ↓)
WE read time (from RAS ↑)
WE read time (from CAS ↑)
WE pulse width
tPC
(2 + wCP + wDA + wF + w) T – 10
(2.5 + wCP + wDA + w) T – 10
(1 + wDA) T – 10
tRHCP
tWCH
tRWL
tCWL
tWP
wCP = 0
wCP = 0
wCP = 0
(1.5 + wDA + w) T – 10
(1 + wDA + w) T – 10
(1 + wDA + w) T – 10
RAS pulse width
tRASP
tWCS1
tWCS2
(2.5 + wRH + wDA + wF + w) T – 10
(1 + wRH + wRP + w) T – 10
wCPT – 10
WE setup time
Off-page
On-page
wCP = 0
(to CAS ↓)
wCP ≥ 1
112
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
