µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3)
TRPW T1 TRHW T2 TDAW TW
T3 TCPW TO1 TDAW TW TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<57>
<56>
<59>
Column address
Row address
<76>
Column address
<64>
<61>
<94>
<60>
<69>
<77>
<65>
<83>
<63>
<66>
<67>
<81>
UCAS (Output)
LCAS (Output)
<70>
<71>
<82>
<96>
<79>
RD (Output)
OE (Output)
<105>
<48>
<97>
DMAAKm (Output)
WE (Output)
<68>
IORD (Output)
IOWR (Output)
D0 to D15 (I/O)
WAIT (Input)
<106>
<42>
<43>
<78>
<37>
<41>
<50>
<24>
Data
Data
<25>
<24>
<24>
<25>
<25>
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 0 to 7, m = 0 to 3
111
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
