µPD703100A-33, 703100A-40, 703101A-33, 703102A-33
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Data output delay time from OE ↑
IOWR ↓ delay time from address
<24>
tSWK
tHKW
10
<25>
<37>
<41>
<42>
2
ns
tDRDOD
tDAWR
tSAWR
(0.5 + i) T – 10
(0.5 + wRP) T – 5
ns
ns
Address setup time
(2 + wRP + wRH + wDA)
T – 10
ns
(to UWR, LWR IOWR ↑)
Address delay time from IOWR ↑
RD ↑ delay time from IOWR ↑
<43>
<48>
tDWRA
0.5T – 5
0
ns
ns
ns
ns
tDWRRD
wF = 0
wF = 1
T – 10
IOWR low-level width
<50>
tWWRL
(2 + wRH + wDA + w)
T – 10
Row address setup time
Row address hold time
Column address setup time
Column address hold time
<56>
<57>
<58>
<59>
tASR
tRAH
tASC
tCAH
(0.5 + wRP) T – 10
(0.5 + wRH) T – 10
0.5T – 10
ns
ns
ns
ns
(1.5 + wDA + wF + w)
T – 10
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA +
wF +w) T – 10
ns
RAS precharge time
RAS hold time
<61>
<63>
tRP
(0.5 + wRP) T – 5
ns
ns
tRSH
(1.5 + wDA + wF + w)
T – 10
Column address read time for RAS
CAS pulse width
<64>
<65>
tRAL
(2 + wCP + wDA + w
F
+ w)
ns
ns
T – 10
tCAS
(1 + wDA + wF + w)
T – 10
CAS-RAS precharge time
CAS hold time
<66>
<67>
tCRP
tCSH
(1 + wRP) T – 10
ns
ns
F
(2 + wRH + wDA + w +w)
T – 10
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
CAS precharge time
<68>
<69>
<70>
<71>
<76>
<77>
tRCS
tRRH
tRCH
tCPN
tRAD
tRCD
(2 + wRP + wRH) T – 10
0.5T – 10
ns
ns
ns
ns
ns
ns
1.5T – 10
(2 + wRP + wRH) T – 5
(0.5 + wRH) T – 10
(1 + wRH) T – 10
RAS column address delay time
RAS-CAS delay time
108
Preliminary Data Sheet U14168EJ2V0DS00
NEC [ NEC ]
